1. Technical Field
This disclosure relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a semiconductor device having a buried contact plug.
2. Description of the Related Art
As electronic products become thinner and smaller, research is actively conducted on high integration technology for semiconductor devices used in electronic products. The high integration technology includes technology for reducing components of the semiconductor devices and technology for effectively arranging components of the semiconductor devices.
For example, a semiconductor memory device such as a dynamic random access memory (DRAM) includes a plurality of memory cells. The memory cell has a cell transistor, a cell capacitor, and an interconnection. A structure having an area of 8F2 is widely employed for the memory cell. In addition, technology for arranging the area of the memory cell to 6F2 or 4F2 is widely researched. In this case, F denotes the minimum feature size. Accordingly, technology for connecting the cell transistor to the cell capacitor is faced with several difficulties.
FIGS. 1 and 2 are cross-sectional views illustrating a method of fabricating a conventional DRAM. Specifically, FIG. 1 is a cross-sectional view taken along the direction crossing a word line, and FIG. 2 is a cross-sectional view taken along the direction crossing a bit line.
Referring to FIGS. 1 and 2, an isolation layer 3 is formed to define active regions 2 in a predetermined region of a semiconductor substrate 1. Gate dielectric layers 5 are formed on the active regions 2. Gate electrodes 7 and passivation layer patterns 9 are formed on the gate dielectric layers 5 which cross the active regions 2 and are sequentially stacked. The gate electrodes 7 extend to act as a word line. Spacers 11 are formed on sidewalls of the gate electrodes 7. A lower inter-level dielectric layer 13 is formed on the entire surface of the semiconductor substrate 1 having the gate electrodes 7. Storage landing pads 15 and bit line landing pads 16 are formed through the lower inter-level dielectric layer 13 to contact the active regions 2. An intermediate inter-level dielectric layer 23 is formed on the semiconductor substrate 1 having the storage landing pads 15 and the bit line landing pads 16. Bit line plugs 19 in contact with the bit line landing pads 16, and bit lines 21 crossing over the bit line plugs 19 are formed within the intermediate inter-level dielectric layer 23. The bit lines 21 are electrically connected to the active regions 2 via the bit line plugs 19 and the bit line landing pads 16. In addition, buried contact plugs 25 in contact with the storage landing pads 15 are formed within the intermediate inter-level dielectric layer 23. Top surfaces of the buried contact plugs 25 are exposed. Intermediate pads 27 are formed on the buried contact plugs 25. An upper inter-level dielectric layer 29 is formed on the semiconductor substrate 1 having the intermediate pads 27. Top surfaces of the intermediate pads 27 are exposed. Storage nodes 31, a capacitor dielectric layer 33, and a plate node 35 are sequentially stacked on the exposed intermediate pads 27. In this case, the storage node 31 acts as a lower electrode of a capacitor, and the plate node 35 acts as an upper electrode of the capacitor. In addition, the storage node 31 is electrically connected to the active region 2 via the intermediate pad 27, the buried contact plug 25, and the storage landing pad 15.
To achieve high integration, it is advantageous that the storage nodes 31 are regularly arranged with a predetermined size. However, the buried contact plugs 25 must be in contact with the storage landing pads 15 to avoid contact with the bit lines 21 and the bit line landing pads 16. In addition, the buried contact plug 25 must be formed to avoid contact with adjacent other storage landing pads 15. It is very difficult to regularly arrange the buried contact plugs 25 in this manner. Consequently, an arrangement margin for the storage nodes 31 must be secured using the intermediate pads 27. In this case, an additional process of forming the intermediate pads 27 is required. In addition, an area loss occurs due to the arrangement margin of the intermediate pads 27.
U.S. Pat. No. 6,136,643 to Jeng, et al. (“Jeng”) is directed at Method for Fabricating Capacitor-Over-Bit-Line Dynamic Random Access Memory using self-aligned contact etching technology.
According to Jeng, the method includes forming a DRAM cell having capacitors of a COB structure along with active regions, gate patterns, and bit line patterns. An etch stopper is formed to cover gate electrodes, sidewall spacers, and source and drain regions. Self-aligned openings are formed to expose the source and drain regions through a first oxide layer. Polysilicon landing plugs are formed to fill the self-aligned openings. A second oxide layer is formed and then a bit line contact hole is formed. A polycide layer and a capping layer are sequentially stacked and patterned to form a bit line. A third etch stopper is formed, and a third oxide layer is formed. A capacitor node opening is formed through the third oxide layer. A capacitor lower electrode, a capacitor dielectric layer, and a capacitor upper electrode are formed. The third etch stopper acts to prevent the third oxide layer from being over-etched while the capacitor node opening is formed. Nevertheless, consistent efforts are required to prevent the contact plug from being electrically connected to its adjacent conductive patterns.
Embodiments of the invention address these and other disadvantages of the conventional art.